NOTE that you can JUST BRIDGE THE 3 PINS TOGETHER ( #48, #49#50) without cutting anything, however you need to make sure that the pins 49(PD6) and 50(PD7) are always defined as inputs :ĭDRD |= (0 << PD6)|(0<<PD7) //sets pins as inputsīEWARE though, if any of the PD5, PD6 or PD7 is defined as output and low while any other is high, it will short them! take a look at digital pin 38, (pin #50, (PD7) at the corner of the chip), it is only 1 pin away from the XCK1 pin ( #48 (PD5)). However, some of the functionality of theĬontrol registers changes when using MSPIM." The I/O register locations are the same in both modes. However, the pin control logic and interrupt generation logic is identical in The USART RX and TX control logic is replaced by a common SPI The parity generator and checker, the data and clock recovery logic, and the RX and TXĬontrol logic is disabled. Resources include the transmitter and receiver shift register and buffers, and the baud rate generator. The SPI master control logic takes direct control over the USART resources. Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic.
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